- Designing of high performance analog circuit.
- Plan and perform silicon engineering validation of the responsible analog circuit. Perform silicon debug. Work with test engineer to plan and determine ATE test plan for the responsible analog circuit.
- Master degree in electrical engineering with 3 years of experience or more, PhD in electrical engineering with 1 years of experience or more. Otherwise, Degree qualified with exceptionally relevant industry experience of 8 years or more may also be considered.
- Good experience in some area of analog designs:
- High speed and low power ADC,
- High linearity and low noise amplifier,
- High linearity and low noise analog filter;
- High performance PLL,
- Low noise OSC,
- High speed SERDES,
- Inductive or capacitive base power converter,
- Low noise LDO,
- High performance temperature sensor,
- Low noise and high accuracy voltage/current reference etc.
- Solid understanding of analog design fundamentals including device physics, analog circuit analysis, sampling theory, control theory and good understanding of communication theory.
- Strong analytical skill and familiar with underline theory for both time domain analysis and frequency domain analysis
- Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations.
- Familiar with both schematic and layout tool, methodologies, flow and CAD tools such as SPICE, Cadence virtuoso, Spectre, PCELL layout, Calibre physical verification.
- Good team work, responsible, good communication skill.
- Higher qualified candidates with solid experience background may be considered for higher grade Engineering position.
We regret that only shortlisted candidates will be notified.
GMP Technologies (S) Pte Ltd | EA Licence: 11C3793 | EA Personnel: Tan Wai Peng | Registration No: R1104671