- Cooperate with R&D department to develop chip circuit test method and ATE test scheme according to chip circuit test requirements and test accuracy requirements, including test plan preparation, LAB&ATE setup, test development schedule, etc.
- Cooperate with R&D department, participate in the formulation and verification of DFT scheme during the chip development phase, evaluate and balance ATE test coverage and test cost.
- Generate ATE test pattern according to chip design specification, develop test schematic diagram and support ATE debug in cooperation with ATE test engineer, and conduct correlation analysis on test data collected by ATE and LAB.
- During the life cycle of the chip, be responsible for continuously improving test coverage and reducing test cost.
- According to the chip characteristics and product line classification, be responsible for standardizing and universalizing the test process and test hardware to improve the efficiency of ATE test development.
- Possess a Bachelor degree major in electronics or related engineering.
- More than 5 years working experience in test development.
- Proficient in 93K, J750 and other mainstream digital/SoC ATE platforms, proficient in Perl or other scripting languages.
- Master Verilog hardware design language and EDA tools such as VCS and Verdi.
- Proficient in digital and mixed signal chip test theory.
- Familiar with chip design process.
- Master basic principles of digital and mixed signal circuits.
- Good communication skills and motivation.
We regret that only shortlisted candidates will be notified.
GMP Technologies (S) Pte Ltd | EA Licence: 11C3793 | EA Personnel: Lim Zi Cheng | Registration No: R2089949