Job Purpose Summary:

The Sr./Staff Digital Frontend Engineer will be responsible for implementing our PHY, switch and SOC ASIC's. You will work closely with our Digital/Analog engineers to turn RTL to netlist, including timing optimization, DFT insertion (JTAG, MBIST, DC/AC mode test) and also final tapeout timing signoff.

Job Profile:

• RTL quality check, confirm the issue found with designer and work out the solution.
• Develop constraints according to clock structure.
• Complete synthesis, point out potential timing risk or possible optimizing point on area, power or test coverage.
• Insert and verify DFT logic, MBIST, SCAN and OCC.
• Research on new DFT methodology, optimize flow.
• Support test pattern generation and debugging for ATE testing.
• Participate in testing and debugging silicon.
• Work with physical design teams for optimizing layout and achieving timing closure on ASIC/SoC designs.
• Support gate-level net-list functional and timing verification activities till tapeout.

Requirements:

• Minimum 6 year of industry experience, MS degree in Microelectronics/Computer engineering.
• Rich knowledge of IC design frontend flows, capable to set script files for required tools.
• Strong DFT background, including Boundary scan, BIST, SCAN, at-speed test etc.
• Experienced in tapeout timing signoff, including OCV setting, report check, issue locating and supply ECO solution.
• Good at low power flow with UPF experience is a plus.

We regret that only shortlisted candidates will be notified.

GMP Technologies (S) Pte Ltd   |   EA Licence: 11C3793   | EA Personnel:  Tan Wai Peng  |   Registration No: R1104671