To provide support to Fab and TD on all FEOL reliability matters including process qualifications, process reliability monitoring and change requests.
Duties and Responsibilities:
- Establish wafer level GOI, PID, HCI, NBTI and TDDB test methodologies and provide reliability design guidelines for IC designers.
- Build up in-house equipment troubleshooting capabilities.
- Design GOI, PID, HCI, NBTI and TDDB test structures for reliability characterization to determine reliability layout rules and models.
- Have ownership of the definitions, documentation and maintenance of test procedures, test findings & tools, plus training of the Reliability staff.
- Implement reliability assessment excellence practices in terms of ESD control, cycle time, data integrity and work procedures documentations.
- Define and execute benchmarked reliability test plan for new process qualification, process reliability monitor (PRM) programs, change requests and line issues.
- Support customer engagement in reliability aspects. Provide reliability presentations for customer visit and audits. Participate in reliability risk assessment meetings with customers.
- Drive for effective CA/PA on GOI, PID, HCI, NBTI and TDDB reliability failures
- Bachelor/ Master / PHD in Engineering or Science or equivalent.
- 4-6 years of relevant experience in reliability tests
- Knowledge of Front-End wafer fabrication is a MUST.
- Knowledge of MOS Device Physics and Reliability Statistics.
- Knowledge of Reliability Test-Chip Layout Design.
- Knowledge of Minitab, JMP, FMEA, 8D, etc, is an advantage.
- Good coaching and problem-solving skills.
- Team player with effective communication skills.
We regret that only shortlisted candidates will be notified.
GMP Technologies (S) Pte Ltd | EA Licence: 11C3793 | EA Personnel: Tan Wai Peng | Registration No: R1104671