Position Description

Senior Process Engineer (Wafer FInishing Process / Semicon BEOL / Yishun)
Job Code 21346
Division GMP TECHNOLOGIES (S) PTE LTD (EA Licence:11C3793)
Job Placement Location Singapore
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Responsibilities:

  • Development, process/product characterization and qualification of Wafer Finishing assigned process for pilot runs and volume ramp within the Singapore Operations.
  • Establishing good process margins and inline controls of these new processes.
  • Creating and updating of process specification and documentation of working procedure.
  • Resolving reliability or yield issues related to the Wafer Break, UV Taping/Detaping, and Pick & Place processes as well as lead trouble-shooting of defect and yield issues and process excursions associated with the new process/tools.
  • Championing engineering experiments for process characterization.
  • Responsible for cost-saving projects. 

Requirements:

  • Bachelor's Degree in Electrical & Electronics Engineering /Mechanical Engineering or Materials  Engineering is required with more than 5 years of work experience in Wafer Backend processes such as Wafer Break (Singulation) and Die Sorting or Die Attach processes.
  • Experience with ASM Die Sorter tools (MS90, MS899, MS100) would be advantageous
  • Good interpersonal skills with good organizational skills and attention to detail.
  • Strong knowledge of SPC and quality tools such as FMEA and Control Plan.
  • Self-driven leader and strong team player with keen technical ability, systematic approach, detailed-oriented, excellent problem-solving skills, and positive attitude.

 

 

We regret that only shortlisted candidates will be notified.

GMP Technologies (S) Pte Ltd  |  EA Licence 11C3793  |  EA Personnel:  Novita Widjaja  |  Registration No: R22105960

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