Position Description

Senior / Layout Engineer (Performance Network Connectivity Silicon/IC Chips)
Job Code 21885
Division GMP TECHNOLOGIES (S) PTE LTD (EA Licence:11C3793)
Job Placement Location Singapore
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Job Tasks :

  • In this role, you will work with our analog design engineers to layout the high speed, high performance analog circuit such as: high speed and low power ADC, high linearity and low noise amplifier, high linearity and low noise analog filter; high performance PLL, low noise OSC, high speed SERDES, inductive or capacitive base power converter, low noise LDO, high performance temperature sensor, low noise and high accuracy voltage/current reference and or IO and ESD cells   etc.
  • Engage in floor planning, die size estimates, block level routing and top level chip assembly.
  • Apply high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electro-migration.
  • Read and interpret Design Rule Manuals.
  • Perform physical layout implementation at block and top levels utilizing best practices for matching, shielding, dummies, fills, and isolation.



  • Degree in Electrical engineering or equivalent, 5 years or more of CMOS analog circuit layout experience.
  • Experience with analog layout for silicon chips in mass production.
  • Ability to layout analog circuitry in a size/time-constrained environment.
  • Understand how to optimize layout to reduce parasitic effect in high speed analog circuit.
  • Understand device matching techniques such as common centroid, matching, and the use of dummy devices, etc.
  • Understand signal conditioning/protection techniques such as shielding, isolation, etc.
  • Understand ESD and Latch-up issues and have experience in good layout practice to prevent ESD and Latch-up issues.
  • Ability to solve design problems while using a combination of technical skills, intuition, and creativity.
  • Proficiency in floor planning activities with block level and top level assembly/routing.
  • LVS troubleshooting and debugging skills.
  • Excellent collaboration skills including written and verbal communication.
  • Layout Experience in 28nm or 40nm and experience in FinFET is preferred.


We regret that only shortlisted candidates will be notified.


GMP Technologies (S) Pte Ltd | EA Licence: 11C3793 | EA Personnel: Tan Wai Peng | Registration No: R1104671

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